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? e95840-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage v cc 7v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 450 mw operating condition supply voltage v cc 4.5 to 5.25 v description the CXA2032Q is a bipolar ic designed as recording/playback amplifiers for 8 mm vtrs. features recording system supports evr control for recording y/low-band recording level feedback damping circuit provided in the recording amplifier playback system feedback damping circuit provided in the playback amplifier facilitates printed circuit board design rfagc and dropout detection circuit applications 8 mm vtr structure bipolar silicon monolithic ic 2-channel rec/pb amplifier for 8 mm vtr 32 pin qfp (plastic) CXA2032Q
2 CXA2032Q block diagram and pin configuration l o g i c b u f f a g c d e t d o c d e t 1 1 7 6 5 4 3 2 8 1 9 1 0 1 1 1 2 1 3 1 4 1 6 1 5 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 r f a g c t c r f a g c o u t d o c d e t d o p b o t h r e c r f s w p r p p b y l e v e l r f a g c i n v r e g p b r f o u t v c c v o u t 1 r e c 1 i n r e c d u m p 1 v c c 1 r e c 1 o u t p b 1 i n g n d 1 p b d u m p 1 p b d u m p 2 g n d 2 p b 2 i n r e c 2 o u t y i n c l e v e l c i n g n d v o u t 2 r e c 2 i n r e c d u m p 2 v c c 2 c x a 2 0 3 2 q r f s w 1 c h 6 d b 2 c h 1 5 d b r e c 1 c h 4 0 d b h e a d r e c 2 n d 4 0 d b 1 5 d b r e c 2 c h h e a d 2 n d r e c y g c a c g c a r f a g c
3 CXA2032Q pin description (v cc , v cc 1ch, v cc 2ch=4.75 v ta=25 c) pin no. 1 2 3 4 symbol ylevel rp pb rfswp both rec 0 v to 4.75 v input h: 2.3 v or more l: 0.6 v or less input h: 2.3 v or more l: 0.6 v or less input h: 2.3 v or more l: 0.6 v or less input description evr adjusting pin for y signal level during recording. the control voltage is from 0 v to 4.75 v. increasing the input voltage increases the y signal level. input pin for rec/pb mode switching signal. h: pb l: rec input pin for rfswp signal. alternate recording/both channel recording switching pin. h: both channel recording l: alternate recording equivalent circuit pin voltage dc ac 7 9 . 5 k 1 4 0 3 7 1 8 0 k 1 4 0 1 0 1 . 4 v 2 8 0 k 1 4 0 1 0 1 . 4 v 3 8 0 k 1 4 0 1 0 1 . 4 v 4
4 CXA2032Q pin no. 5 6 7 8 symbol dop docdet rfagcout rfagctc pin voltage dc ac h: 3.15 v l: 0.0 v output 2.6 v (when pin is open) 2.8 v 2.5 v to 4.75 v input (during evr adjustment) 400mvp-p output equivalent circuit 1 5 0 2 . 4 k 3 . 1 v 5 4 . 1 5 v 5 0 1 4 0 2 6 . 3 k 4 3 . 4 k 6 6 0 0 1 0 0 4 0 4 1 0 7 5 0 5 0 2 5 2 5 1 4 0 8 description output pin for dropout detection signal. goes high during dropout. pin for deciding dropout detection level. connect decoupling capacitance between this pin and gnd. for adjustment, input voltage proportional to pin 10 (vreg) output voltage. increasing the input voltage increases the detection level. output pin for playback y signal. rfagc time constant pin. rfagc gain can be adjusted by evr. increasing the input voltage increases the gain. v c c 4 7 0 0 p 8 4 7 0 k
5 CXA2032Q pin no. 9 10 11 12 symbol rfagcin vreg pbrfout v cc pin voltage dc ac 4.15 v 2.0 v 4.75 v 220mvp-p input 220mvp-p (playback y signal output) equivalent circuit 5 0 k 5 0 1 4 0 1 3 p 3 . 2 5 v 9 1 0 3 6 0 1 0 0 3 5 2 9 0 1 1 description input pin for playback y signal. playback y signal is separated from playback video signal output to pin 11 (pbrfout), then input to pin 9 (rfagcin). output pin for 4.15 v regulator. connect decoupling capacitance between this pin and gnd. output pin for playback video signal. power supply pin for main blocks excluding recording and head amplifiers.
6 CXA2032Q pin no. 13 14 15 16 symbol vout1 rec1in recdump1 v cc 1 pin voltage dc ac 3.4 v 0.7 v 1.4 v 4.75 v 184mvp-p (recording y signal output) 120 ap-p input equivalent circuit 1 5 0 1 0 0 4 0 0 1 3 1 0 0 3 0 0 3 0 0 1 0 0 1 4 7 . 5 k 7 . 5 k 7 . 5 k 4 . 1 5 v 1 5 description recording video signal 1ch output pin. the signal obtained by mixing the recording y, recording c, recording afm and recording atf signals is output. recording video signal 1ch rec amp input pin. pin 13 (vout1) output is v/i converted by external resistor, then input to pin 14 (rec1in). damping adjusting pin for 1ch recording amplifier. damping is adjusted by attaching damping resistor between pin 15 and gnd. decreasing the resistance value increases the damping. power supply pin for 1ch recording and head amplifiers.
7 CXA2032Q pin no. 17 18 19 20 symbol rec1out pb1in gnd1 pbdump1 pin voltage dc ac 16.5 ma output 0.7 v 0 v 2.6 v 19 map-p output 200 vp-p input equivalent circuit 1 6 . 5 m 1 0 0 1 7 1 . 2 m 1 . 5 v 1 8 2 7 0 1 2 0 1 3 0 4 0 2 0 description recording signal 1ch output pin. this pin is an open collector. playback signal 1ch input pin. gnd pin for 1ch recording and head amplifiers. damping adjusting pin for 1ch head amplifier.
8 CXA2032Q pin no. 21 22 23 24 symbol pbdump2 gnd2 pb2in rec2out pin voltage dc ac 2.6 v 0 v 0.7 v 16.5 ma output 200 vp-p input 19 map-p output equivalent circuit 2 7 0 1 2 0 1 3 0 4 0 2 1 1 . 5 v 1 . 2 m 2 3 1 6 . 5 m 1 0 0 2 4 description damping adjusting pin for 2ch head amplifier. gnd pin for 2ch recording and head amplifiers. playback signal 2ch input pin. recording signal 2ch output pin. this pin is an open collector.
9 CXA2032Q pin no. 25 26 27 28 symbol v cc 2 recdump2 rec2in vout2 pin voltage dc ac 4.75 v 1.4 v 0.7 v 3.4 v 120 ap-p input 184mvp-p (recording y signal output) equivalent circuit 7 . 5 k 7 . 5 k 7 . 5 k 4 . 1 5 v 2 6 1 0 0 3 0 0 3 0 0 1 0 0 2 7 1 5 0 1 0 0 4 0 0 2 8 description power supply pin for 2ch recording and head amplifiers. damping adjusting pin for 2ch recording amplifier. damping is adjusted by attaching damping resistor between pin 26 and gnd. decreasing the resistance value increases the damping. recording video signal 2ch rec amp input pin. pin 28 (vout2) output is v/i converted by external resistor, then input to pin 27 (rec2in). recording video signal 2ch output pin. the signal obtained by mixing the recording y, recording c, recording afm and recording atf signals is output.
10 CXA2032Q pin no. 29 30 31 32 symbol gnd cin clevel yin pin voltage dc ac 0 v 3.45 v 0.0 v to 4.75 v input 3.05 v 136mvp-p (recording c signal input) 500mvp-p equivalent circuit 2 5 1 4 0 3 . 4 5 v 2 5 5 0 k 5 0 k 3 0 7 9 . 5 k 1 4 0 3 7 3 1 1 4 0 1 0 0 5 0 k 3 . 0 5 v 5 0 k 3 2 description gnd pin for main blocks excluding recording and head amplifiers. input pin for recording c, recording afm and recording atf signals. these three signals are mixed by external resistor, then input to pin 30 (cin). evr adjusting pin for low- band recording signal (c, afm, atf) level. the control voltage is from 0 v to 4.75 v. increasing the input voltage increases the low- band recording signal level. input pin for recording y signal.
11 CXA2032Q electrical characteristics target values * see the control logic truth table for control logic. (v cc =4.75 v, ta=25 c, see the electrical characteristics measurement circuit.) no. 1 2 3 4 5 6 7 8 9 10 11 item circuit current during recording circuit current during playback vreg pin voltage recording y signal gca minimum gain recording y signal gca maximum gain recording y signal gca frequency response (center) recording y signal gca secondary distortion (center gain) recording c signal gca minimum gain recording c signal gca maximum gain recording c signal gca frequency response (center) recording c signal gca secondary distortion (maximum gain) symbol i rec i pb v reg g ymin g ymax v fy dy g cmin g cmax vfc dc measurement conditions input conditions pin level frequency 32 1120 mvp-p 300 khz 32 225 mvp-p 300 khz 32 500 mvp-p 10 mhz 32 500 mvp-p 7 mhz 30 305 mvp-p 300 khz 30 60 mvp-p 300 khz 30 136 mvp-p 2 mhz 30 90 mvp-p 700 khz log ic b f b b b b b b b b b measurement pin or ammeter name i v cc iv cc 10 13 13 13 13 13 13 13 13 measurement method current consumption inside ic during switching recording * 1 current consumption inside ic during playback pin voltage measurement pin 1 (ylevel) = 0 v pin 1 (ylevel) = 4.75 v 10 mhz level/300 khz level pin 1 (ylevel) = vylev (center gain) pin 1 (ylevel) = vylev (center gain) pin 31 (clevel) = 0 v pin 31 (clevel) = 4.75 v 2 mhz level/300 khz level pin 31 (clevel) = cylev (center gain) pin 31 (clevel) = 4.75 v min. typ. max. 20 29 38 16 23 30 3.95 4.15 4.35 ?7.2 ?5.7 ?.7 0.9 ?.3 ?.3 0.7 ?0 ?7.8 ?6.4 ?.4 0.6 ?.5 0 0.5 ?6 unit ma ma v db db db db db db db db recording system ( * 1: including recording amplifier 1ch output bias current)
12 CXA2032Q no. 12 13 14 15 16 17 18 19 20 21 22 23 item recording afm signal secondary distortion (maximum gain) recording amplifier output bias current recording amplifier output current recording amplifier frequency response playback amplifier, rfsw gain rfagc standard output rfagc cover range high rfagc cover range low dropout detection on level dropout detection off level dropout pulse low level dropout pulse high level symbol d afm ib1, 2 i r1 i r2 ? r1 ? r2 gv1 gv2 v agc1 v agc2 v agc3 k do-on k do-off v dop-l v dop-h measurement conditions input conditions pin level frequency 30 90 mvp-p 1.7 mhz 14 184 mvp-p 1 mhz 27 184 mvp-p 1 mhz 14 184 mvp-p 10 mhz 27 184 mvp-p 10 mhz 18 200 vp-p 300 khz 23 200 vp-p 300 khz 9 224 mvp-p 7 mhz 9 56 mvp-p 7 mhz 9 896 mvp-p 7 mhz see measurement method (figure to right). log ic b b b b b b f e f f f f f f f measurement pin or ammeter name 13 ib1, 2 17 24 17 24 11 11 7 7 7 5 5 5 5 measurement method pin 31 (clevel) = 4.75 v dc current measurement output level (mvp-p)/51 output level (mvp-p)/51 10 mhz level/1 mhz level 10 mhz level/1 mhz level measure output level, applying time constant to pin 8 (rfagctc). apply time constant to pin 8 (rfagctc). min. typ. max. ?5 12.7 16.5 20.2 16.6 19 21.4 0 57.9 61.4 64.9 330 400 470 310 375 425 495 ?3.5 ?0.5 ?.5 ?.5 ?.5 ?.5 0 0.01 0.2 2.9 3.15 3.4 unit db ma ma p-p db db mv p-p db v playback system v d o p - l v d o p - h k d o - o n = 2 0 l o g ( a / 2 2 4 ) k d o - o f f = 2 0 l o g ( b / 2 2 4 ) p i n 9 i n p u t p i n 5 o u t p u t 1 0 k h z 7 m h z 2 2 4 m v p - p a b
13 CXA2032Q no. 24 25 item dropout on detection time dropout off detection time symbol t dop -on t dop -off measurement conditions input conditions pin level frequency see measurement method (figure to right). log ic f f measurement pin or ammeter name 5 5 measurement method apply time constant to pin 8 (rfagctc). min. typ. max. 1 2 unit s t d o p - o f f t d o p - o n p i n 9 i n p u t p i n 5 o u t p u t 5 0 s e c 5 k h z 7 m h z / 2 2 4 m v p - p
14 CXA2032Q control logic truth table 2 3 4 13 28 17 24 11 7 l l l v v ? v l h l v v v ? l l h v v v v l h h v v v v h l o o ch2 o o h h o o ch1 o o a b c d e f mode rec pb operation video each rec video both rec pb control logic input conditions operation of each section under respective input conditions recording system playback system input conditions and operation name of control logic conditions (description of input conditions) h ? ? control logic input voltage of 2.3 v or more l ? ? control logic input voltage of 0.6 v or less ? ? ? don? care. (description of operation mode) o ? ? operating ? ? ? operating but bias current is off. ? ? not operating ch1 ? ? ch1 signal is output. v ? ? video signal is output. ch2 ? ? ch2 signal is output. r p p b r f s w p b o t h r e c v o u t 1 v o u t 2 r e c 1 o u t r e c 2 o u t p b 1 c h a m p p b 2 c h a m p p b r f o u t r f a g c o u t d o c d e t
15 CXA2032Q electrical characteristics measurement circuit 5 . 6 0 . 0 1 h e a d 2 n d r e c r e c h e a d 0 . 0 2 2 0 . 0 2 2 3 9 0 3 9 0 5 . 6 0 . 0 1 g n d 1 p b d u m p 1 p b d u m p 2 g n d 2 g n d g n d 1 1 4 9 4 9 p b 1 i n p b 2 i n p b 1 i n p b 2 i n l o g i c b u f f r f a g c a g c d e t d o c d e t r e c 1 o u t r e c 2 o u t r e c 1 o u t r e c 2 o u t r e c 1 c h 4 0 d b 1 5 d b 1 c h 2 c h r f s w 6 d b 4 0 d b 1 5 d b r e c 2 c h g n d y l e v e l b o t h r e c r f s w p r p p b . c g c a y g c a v r e g p b r f o u t v o u t 1 r e c 1 i n r e c d u m p 1 v c c 1 0 . 0 1 r f a g c i n g n d 0 . 0 1 1 0 0 . 1 g n d 1 0 1 0 g n d p b r f o u t v o u t 1 r e c 1 i n 1 . 5 k 0 . 0 1 4 7 k 5 1 g n d 1 5 k y i n c i n y i n c l e v e l c i n g n d v o u t 2 r e c 2 i n r e c d u m p 2 0 . 0 1 g n d g n d 5 1 5 1 0 . 0 1 c l e v e l g n d 5 1 g n d v o u t 2 r e c 2 i n 5 1 4 7 k 1 . 5 k 0 . 0 1 g n d 1 0 0 1 0 0 . 1 g n d 5 1 5 1 1 0 0 1 0 0 . 1 g n d 1 5 k g n d 2 n d c x a 2 0 3 2 q 4 . 7 5 v g n d i b 2 i b 1 1 1 0 . 0 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 c o n t r o l l o g i c p i n e v r a d j u s t i n g p i n s i g n a l o u t p u t p i n ( m e a s u r e m e n t p o i n t ) s i g n a l i n p u t p i n ( s i g n a l s o u r c e i m p e d a n c e 5 0 w ) 4 7 0 0 p 4 7 0 k 0 . 0 1 r f a g c t c g n d r f a g c o u t 0 . 1 d o p g n d 0 . 0 1 r f a g c t c r f a g c o u t d o c d e t d o p b o t h r e c r f s w p r p p b y l e v e l r f a g c i n v c c a a a i v c c g n d v c c 2 h e a d a m p l i f i e r i n p u t ( p b 1 i n , p b 2 i n ) : t h e i n p u t l e v e l i s s p e c i f i e d b y a v a l u e a t t e n u a t e d t o 1 / 5 0 .
16 CXA2032Q application circuit r e c y r f c o n t r o l l o g i c l o g i c b u f f r f a g c r e c 1 c h 4 0 d b 1 5 d b 1 c h 2 c h r f s w 6 d b 4 0 d b 1 5 d b r e c 2 c h c g c a y g c a c x a 2 0 3 2 q 1 5 k 0 . 0 1 1 . 5 k 4 7 k 1 0 0 . 1 1 0 0 1 0 0 . 1 1 0 0 . 1 1 0 a g c d e t r f a g c t c r f a g c o u t d o c d e t d o p b o t h r e c r f s w p r p p b y l e v e l 4 7 0 0 p 4 7 0 k 0 . 1 0 . 0 1 d o c d e t y / c s e p y c 0 . 1 r e c 1 5 k r e c r e c d u m p r e c 2 i n v o u t 2 g n d c i n c l e v e l y i n 0 . 0 1 1 . 5 k 4 7 k 0 . 1 3 . 3 k 3 . 3 k 0 . 1 0 . 1 2 k 0 . 0 1 0 . 0 1 r e c 1 o u t p b 1 i n g n d 1 p b d u m p 1 p b d u m p 2 g n d 2 p b 2 i n r e c 2 o u t h e a d 2 n d 0 . 0 1 0 . 0 2 2 3 9 0 0 . 0 2 2 3 9 0 0 . 0 1 h e a d 2 n d 1 0 0 . 1 1 0 0 1 1 2 c h h e a d 8 7 6 5 4 3 2 1 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 s i g n a l o u t e v r c o n t r o l s i g n a l i n p b r f p b c r f p b y r f d o p b o t h r e c r f s w p r p p b y l e v e l c l e v e l r e c c r f r e c a t f r e c a f m v c c 1 c h h e a d v c c 2 r p v c c r p g n d 1 0 r f a g c i n v r e g p b r f o u t v o u t 1 r e c 1 i n r e c d u m p 1 v c c 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
17 CXA2032Q description of operation y, chroma, afm and atf signals are adjusted at specified levels so that they are mixed internally to achieve an appropriate value at the head, then output to pins 13 (vout1) and 28 (vout2). the y level is evr adjusted at pin 1 (ylevel) and the low-band level (chroma, afm, atf) at pin 31 (clevel). the signal, which underwent recording level adjustment, is v/i converted by external resistor, then input to pins 14 (rec1in) and 27 (rec2in). the current of the input signal is amplified by the recording amplifier, and this signal is then output from pins 17 (rec1out) and 24 (rec2out) to drive the head. a feedback damping circuit is incorporated into the recording amplifier to inhibit head resonance, and the peaking amount can be adjusted by external resistors attached to pins 15 (recdump1) and 26 (recdump2). during recording, the output capacitance is about 12 pf including that of the playback amplifier. the playback signal from the head is amplified with low noise and high gain. a feedback damping circuit is incorporated to inhibit head resonance, and the peaking amount can be adjusted by external resistors attached to pins 20 (pbdump1) and 21 (pbdump2). during playback, the output capacitance is approximately 20 pf including that of the recording amplifier. this section switches the playback signals of channels 1 and 2 at the correct timing and outputs the playback video signal to pin 11 (pbrfout). switching is performed at pin 3 (rfswp). this section inputs the playback y signal separated from playback video signal using an external circuit and outputs it at a constant level of 400 mvp-p. a dropout is detected in the playback y signal, and a dropout pulse is output. the detection level is optimized using 224 mvp-p input as a reference. in order to save power consumption, this ic exercises power-saving control of circuit blocks which are not in need for operation depending on the mode. the ic also incorporates a logic circuit for controlling the built-in switches which change inputs and outputs. the combinations of input and output required for basic operation are shown in the control logic truth table. vreg 4.15 v is generated as the reference voltage used in the ic.
18 CXA2032Q notes on operation 1. this ic is characterized by high-voltage gain (approximately 61 db in the playback system). be careful of the following when using the ic. 1) use a reinforced power supply and ground lines. decouple the power supply pin with a coil and a capacitor. connect each decoupling capacitor as close to the pin as possible. 2) use of a regulator power supply is recommended. 3) connecting a capacitive load to the output may cause oscillation. 4) take particular care not to make capacitive coupling between the head amplifier input and the playback output. also be careful not to make capacitive coupling between the recording input and the recording amplifier output. 5) use of decoupling capacitors is recommended between the following dc voltage input pins and gnd. when the control voltage source is at high impedance, aggravation of cross talk or oscillation may occur. pin 1 (ylevel), pin 31 (clevel) 6) when a decoupling capacitor is necessary for other pins (not power supply pin), it is recommended to connect each decoupling capacitor as close to the pin as possible. 7) the voltage input to evr adjusting pins should be proportional to the supply voltage v cc . control the input voltage in the range from 0 to 4.75 v when v cc = 4.75 v. for evr adjustment at pin 8 (rfagctc), control the input voltage in the range of 2.5 v to 4.75 v.
19 CXA2032Q characteristics graphs 1 2 3 4 5 1 8 1 6 1 4 1 2 1 0 8 6 4 2 0 2 ( d b ) y s i g n a l g c a g a i n c o n t r o l p i n 1 ( y l e v e l ) v o l t a g e ( v ) p i n 3 2 ( y i n ) ? p i n 1 3 ( v o u t 1 ) a n d p i n 2 8 ( v o u t 2 ) i / o g a i n 1 2 3 4 5 1 8 1 6 1 4 1 2 1 0 8 6 4 2 0 2 ( d b ) c s i g n a l g c a g a i n c o n t r o l p i n 3 1 ( c l e v e l ) v o l t a g e ( v ) p i n 3 0 ( c i n ) ? p i n 1 3 ( v o u t 1 ) a n d p i n 2 8 ( v o u t 2 ) i / o g a i n 3 . 0 3 . 5 4 . 0 4 . 5 0 1 0 2 0 ( d b ) r f a g c g a i n c o n t r o l p i n 8 ( r f a g c t c ) v o l t a g e ( v ) p i n 9 ( r f a g c i n ) ? p i n 7 ( r f a g c o u t ) i / o g a i n 4 . 7 5 v c c = 4 . 7 5 v v i n = 2 2 5 m v p - p 3 0 0 k h z v c c = 4 . 7 5 v v i n = 6 0 m v p - p 1 0 0 k h z ( w i t h e v r a d j u s t m e n t a t p i n 8 ) 1 0 2 . 5 v c c = 4 . 7 5 v v i n = 5 0 m v p - p 7 m h z
s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y 3 2 p i n q f p ( p l a s t i c ) 9 . 0 0 . 2 7 . 0 0 . 1 1 . 5 0 . 1 5 ( 8 . 0 ) 0 . 1 0 . 1 + 0 . 2 + 0 . 3 5 + 0 . 3 0 . 5 0 0 . 1 2 7 0 . 0 5 + 0 . 1 0 t o 1 0 0 . 8 0 . 3 0 . 1 + 0 . 1 5 1 8 9 3 2 1 6 1 7 2 4 2 5 m 0 . 2 4 0 . 2 g q f p - 3 2 p - l 0 1 q f p 0 3 2 - p - 0 7 0 7 0 . 1 package outline unit : mm CXA2032Q 20

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